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|Title:||Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions’ architectures||Authors:||Michail, Harris
Athanasiou, George S.
Goutis, Costas E.
|Keywords:||Concurrent Error Detection;Cryptography;Hash functions;SHA-1;SHA-256;Totally Self-Checking||Category:||Electrical Engineering - Electronic Engineering - Information Engineering||Field:||Engineering and Technology||Issue Date:||1-Sep-2016||Publisher:||Elsevier||Source:||Microprocessors and Microsystems, 2016, Volume 45, Pages 227-240||metadata.dc.doi:||http://dx.doi.org/10.1016/j.micpro.2016.05.011||Abstract:||Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec and VPN's utilize hash functions - a special family of cryptographic algorithms. Hardware implementations of cryptographic hash functions provide high performance and increased security. However, potential faults during their normal operation cause significant problems in the authentication procedure. Hence, the on-time detection of errors is of great importance, especially when they are used in security-critical applications, such as military or space. In this paper, two Totally Self-Checking (TSC) designs are introduced for the two most-widely used hash functions: SHA-1 and SHA-256. To the best of authors’ knowledge, there is no previously published work presenting TSC hashing cores. The achieved fault coverage is 100% in the case of odd erroneous bits. The same coverage is achieved for even erroneous bits, if they are appropriately spread. Additionally, experimental results in terms of frequency, area, throughput, and power consumption are provided. Compared to the corresponding Duplicated with Checking (DWC) architectures, the proposed TSC-based designs are more efficient in terms of area, throughput/area, and power consumption. Specifically, the introduced TSC SHA-1 and SHA-256 cores are more efficient by 16.1% and 20.8% in terms of area and by 17.7% and 23.3% in terms of throughput/area, respectively. Also, compared to the corresponding DWC architectures, the proposed TSC-based designs are on average almost 20% more efficient in terms of power consumption.||URI:||http://ktisis.cut.ac.cy/handle/10488/9346||ISSN:||01419331||Rights:||© 2016 Elsevier B.V.||Type:||Article|
|Appears in Collections:||Άρθρα/Articles|
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