Please use this identifier to cite or link to this item: http://ktisis.cut.ac.cy/handle/10488/9341
Title: Hardware implementation of the Totally Self-Checking SHA-256 hash core
Authors: Michail, Harris 
Kotsiolis, Apostolis 
Kakarountas, Athanasios P. 
Athanasiou, George S. 
Goutis, Costas E. 
Keywords: Concurrent Error Detection;Cryptography;Hash Functions;Safety;Security;Totally Self-Checking Circuit
Category: Electrical Engineering - Electronic Engineering - Information Engineering
Field: Engineering and Technology
Issue Date: 30-Oct-2015
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: International Conference on Computer as a Tool, IEEE EUROCON 2015; Salamanca; Spain; 8 September 2015 through 11 September 2015
metadata.dc.doi: 10.1109/EUROCON.2015.7313715
Abstract: Hashing cores are utilized by many existing high performance cryptographic systems, used in security schemes such as SET, PKI, and IPSec. Efficient operation of these hardware modules can be degraded, especially when they operate in harsh environments i.e. space applications, military or medical applications. In this paper, a Totally Self-Checking (TSC) design is introduced for the SHA-256 hash function, suitable for harsh environments. The achieved fault coverage is 100% in the case of odd erroneous bits. The same coverage is achieved for even number of erroneous bits, if they are appropriately propagated. Performance measurements are reported for ASIC and reconfigurable technologies, highlighting issues that must be respected by the designer. The introduced TSC hashing core is area-efficient by 19%, compared to the corresponding Duplicated with Checking (DWC) one.
URI: http://ktisis.cut.ac.cy/handle/10488/9341
ISBN: 978-147998569-2
Rights: © 2015 IEEE.
Type: Conference Papers
Appears in Collections:Δημοσιεύσεις σε συνέδρια/Conference papers

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