Please use this identifier to cite or link to this item:
Title: A holistic approach towards intelligent hotspot prevention in network-on-chip-based multicores
Authors: Soteriou, Vassos 
Theocharides, Theocharis 
Kakoulli, Elena 
Keywords: Multiprocessor interconnection
Neural network hardware
On-chip network
Ultra-scale integration
Issue Date: 1-Mar-2016
Publisher: IEEE Computer Society
Source: IEEE Transactions on Computers, 2016, Volume 65, Issue 3, Article number 7110592, Pages 819-833
Abstract: Traffic hotspots, a severe form of network congestion, can be caused unexpectedly in a network-on-chip (NoC) due to the immanent spatio-temporal unevenness of application traffic. Hotspots reduce the NoC's effective throughput, where in the worst-case scenario, network traffic flows can be frozen indefinitely. To alleviate this problematic phenomenon several adaptive routing algorithms employ online load-balancing schemes, aiming to reduce the possibility of hotspots arising. Since most are not explicitly hotspot-agnostic, they cannot completely prevent hotspot formation(s) as their reactive capability to hotspots is merely passive. This paper presents a pro-active Hotspot-Preventive Routing Algorithm (HPRA) which uses the advance knowledge gained from network-embedded artificial neural network-based (ANN) hotspot predictors to guide packet routing in mitigating any unforeseen near-future hotspot occurrences. First, these ANN-based predictors are trained offline and during multicore operation they gather online statistical data to predict about-to-be-formed hotspots, promptly informing HPRA to take appropriate hotspot-preventive action(s). Next, in a holistic approach, additional ANN training is performed with data acquired after HPRA interferes, so as to further improve hotspot prediction accuracy; hence, the ANN mechanism does not only predict hotspots, but is also aware of changes that HPRA imposes upon the interconnect infrastructure. Evaluation results, including utilizing real application traffic traces gathered from parallelized workload executions onto a chip multiprocessor architecture, show that HPRA can improve network throughput up to 81 percent when compared with prior-art. Hardware synthesis results affirm the HPRA mechanism's moderate overhead requisites.
ISSN: 00189340
Rights: © 1968-2012 IEEE
Appears in Collections:Άρθρα/Articles

Show full item record

Page view(s) 50

Last Week
Last month
checked on Aug 21, 2017

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.