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|Title:||A parameterized genetic algorithm ip core design and implementation||Authors:||Deliparaschos, Kyriakos M.
Tzafestas, Spyros G.
|Keywords:||Field programmable gate array (fpga) chip;Genetic algorithm (ga);Intellectual property (ip) core;Travelling salesman problem (tsp);Very high-speed integrated circuits description language (vhdl)||Category:||Electrical Engineering - Electronic Engineering - Information Engineering||Field:||Engineering and Technology||Issue Date:||May-2007||Source:||4th International Conference on Informatics in Control, Automation and Robotics, 2007, Angers, France, 9-12 May||Abstract:||Genetic Algorithm (GA) is a directed random search technique working on a population of solutions and based on natural selection. However, its convergence to the optimum may be very slow for complex optimization problems, especially when the GA is software implemented, making it difficult to be used in real time applications. In this paper a parameterized GA Intellectual Property (IP) core is designed and implemented on hardware, achieving impressive time-speedups when compared to its software version. The parameterization stands for the number of population individuals and their bit resolution, the bit resolution of each individual's fitness, the number of elite genes in each generation, the crossover and mutation methods, the maximum number of generations, the mutation probability and its bit resolution. The proposed architecture is implemented in a Field Programmable Gate Array Chip (FPGA) with the use of a Very-HighSpeed Integrated Circuits Hardware Description Language (VHDL) and advanced synthesis and place and route tools. The GA discussed in this work achieves a frequency rate of 92 MIIz and is evaluated using the Traveling Salesman Problem (TSP) as well as several benchmarking functions.||URI:||http://ktisis.cut.ac.cy/handle/10488/8473||Type:||Conference Papers|
|Appears in Collections:||Δημοσιεύσεις σε συνέδρια/Conference papers|
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