Please use this identifier to cite or link to this item: http://ktisis.cut.ac.cy/handle/10488/8200
Title: A parameterised genetic algorithm IP core: FPGA design, implementation and performance evaluation
Authors: Doyamis, G. C. 
Tzafestas, Spyros G. 
Deliparaschos, Kyriakos M. 
Keywords: Genetic algorithm
Travelling salesman problem
Field programmable gate array chip
Very high-speed integrated-circuits description language
Intellectual property core
Issue Date: 2008
Publisher: Taylor & Francis
Source: International Journal of Electronics, 2008, Volume 95, Issue 11, Pages 1149-1166
Abstract: Genetic algorithm (GA) is a directed random search technique working on a population of solutions and is based on natural selection. However, its convergence to the optimum may be very slow for complex optimisation problems, especially when the GA is software-implemented, making it difficult to be used in real-time applications. In this article, a parameterised GA intellectual property core is designed and implemented on hardware, achieving impressive time-speedups when compared to its software version. The parameterisation stands for the number of population individuals and their bit resolution, the bit resolution of each individual’s fitness, the number of elite genes in each generation, the crossover and mutation methods, the maximum number of generations, the mutation probability and its bit resolution. The proposed architecture is implemented in a field programmable gate array chip with the use of a very high-speed integratedcircuits hardware description language and advanced synthesis and place and route tools. The GA discussed in this work achieves a frequency rate of 92 MHz and is evaluated using the ‘travelling salesman problem’ as well as several benchmarking functions.
URI: http://172.16.21.8/jspui/handle/10488/8200
ISSN: 1362-3060
DOI: 10.1080/00207210802387494
Rights: © Taylor & Francis
Appears in Collections:Άρθρα/Articles

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