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|Title:||Αρχιτεκτονική σχεδίαση, υλοποίηση και εφαρμογή ευφυών αλγορίθμων ελέγχου σε ψηφιακά συστήματα VLSI||Other Titles:||Design architecture, implementation and application of intelligent control algorithms in digital VLSI systems||Authors:||Deliparaschos, Kyriakos M.||Keywords:||Λογική
Γλώσσες περιγραφής υλικού
Πρόβλημα πλανόδιου πωλητή
|Issue Date:||2010||Publisher:||Εθνικό Μετσόβιο Πολυτεχνείο||Abstract:||Software implementations of intelligent control algorithms suffer slow execution time and increased resources demand. Referring to Genetic Algorithms, convergence to the optimal point can prove extremely time-consuming for hard or complex optimization problems, hence not allowing their use in real-time applications. Therefore, it is obvious that applying these algorithms, implemented in software, in real-time robotic applications is practically unfeasible. Based on the last fact, and the fast growth in digital circuit technology, a large number of research work dealing with intelligent control algorithms in programmable logic chips such as Field Programmable Gate Arrays or FPGAs, have been conducted and published over the last few years.The implementation of such algorithms in hardware, offers a substantial increase of data processing speed due to the inherent parallelism of the logic resources into the FPGA that allows for considerable computational throughput, thus rendering them capable of being used in real-time and increased computational complexity applications. Various intelligent algorithm cores can be easily combined with other core modules (e.g., microprocessor core) in order to form a System on a Chip (SoC), which it can be part of an autonomous robotic platform. Moreover, these cores could be used in future applications, thus increasing design re-usability. Finally, intelligent control algorithms implementation on FPGA devices helps to secure reduced power consumption, size, and cost, operation in harsh environments, and easy transfer to structured Application Specific Integrated Circuits (ASICs) if necessary. In this work, several new architectures for the design of intelligent control algorithms are proposed, specifically fuzzy controllers and genetic algorithm cores with the use of Hardware Description Languages (HDLs) and Electronic Design Automation (EDA) tools. In particular, the architectural design and implementation of a parameterized zero-order Takagi-Sugeno Digital Fuzzy Controller (DFLC) core that processes only the active rules is presented which achieves a high clock frequency. Thereinafter, a modified version of the DFLC is presented using a method that increases the parallelism of the architecture and achieves twice the data processing rate of the first core, by processing more than one active rule at the input of the controller per clock cycle. The fuzzy controller core was successfully bound with a microprocessor core and other secondary modules into a SoC to be eventually integrated in a robotic platform for path tracking problems. This SoC offers increased data processing and flexible hardware for different tasks. The SoC was embodied onto a Pioneer P3-DX8 mobile robot and several experiments were performed to evaluate the system’s overall performance. Finally in this work the design, implementation and performance evaluation of a Genetic Algorithm (GA) core is being analyzed. The GA core presented here possesses a high frequency of operation and logic design parallelism, allowing it to be effectively used in real-time applications. The core was evaluated using several benchmarking functions and solving the Travelling Salesman Problem (TSP) for a different number of cities.||Description:||Διδακτορική Διατριβή--Εθνικό Μετσόβιο Πολυτεχνείο||URI:||http://172.16.21.8/jspui/handle/10488/8179|
|Appears in Collections:||Βιβλία/Books|
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