Please use this identifier to cite or link to this item:
Title: Implementation of HSSec: a high-speed cryptographic co-processor
Authors: Michail, Harris 
Kakarountas, Athanasios P.
Goutis, Costas E.
Keywords: Cryptography;Application software;Household electronics;Systems analysis
Issue Date: 2007
Publisher: IEEE
Source: IEEE Symposium on Emerging Technologies and Factory Automation ETFA, 2007, Pages 625-631
Abstract: In this paper a high-speed cryptographic co-processor, named HSSec, is presented. The core embeds two hash functions, SHA-1 and SHA-512, and the symmetric block cipher AES. The architecture of HSSec renders it suitable for widely spread applications with security demands. The presented co-processor can be used inevery system integrating standards such as IPSec or the upcoming JPSec and P1619. The main characteristic of the proposed implementation is common use of the available resources, to minimize further area requirements. Additionally the cryptographic primitives can operate in parallel, providing high throughput whenever needed. Finally the system can operate in ECB or CBC modes. The HSSec co-processor has relatively small area and its performance reaches 1 Gbps (AES, SHA-1 and SHA-512) for XILINX's Virtex II FPGA family.
ISBN: 978-142440826-9
DOI: 10.1109/EFTA.2007.4416827
Rights: © 2007 IEEE
Type: Book Chapter
Appears in Collections:Κεφάλαια βιβλίων/Book chapters

Show full item record

Page view(s) 50

Last Week
Last month
checked on Feb 18, 2019

Google ScholarTM



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.