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|Title:||A top-down design methodology for ultrahigh-performance hashing cores||Authors:||Michail, Harris
Kakarountas, Athanasios P.
Milidonis, Athanasios S.
|Keywords:||Integrity;Authentication;Cryptography;Hardware||Issue Date:||2009||Publisher:||IEEE||Source:||IEEE Transactions on Dependable and Secure Computing, 2009, Volume 6, Issue 4, Pages 255-268||Abstract:||Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec, and VPNs utilize hash functions, which form a special family of cryptographic algorithms. Applications that use these security schemes are becoming very popular as time goes by and this means that some of these applications call for higher throughput either due to their rapid acceptance by the market or due to their nature. In this work, a new methodology is presented for achieving high operating frequency and throughput for the implementations of all widely usedand those expected to be used in the near futurehash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, SHA-512, and so forth. In the proposed methodology, five different techniques have been developed and combined with the finest way so as to achieve the maximum performance. Compared to conventional pipelined implementations of hash functions (in FPGAs), the proposed methodology can lead even to a 160 percent throughput increase.||URI:||http://ktisis.cut.ac.cy/handle/10488/7313||ISSN:||15455971||DOI:||10.1109/TDSC.2008.15||Rights:||© 2009 IEEE||Type:||Article|
|Appears in Collections:||Άρθρα/Articles|
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