Please use this identifier to cite or link to this item: http://ktisis.cut.ac.cy/handle/10488/7305
Title: Improved throughput bit-serial multiplier for GF(2m) fields
Authors: Michail, Harris 
Selimis, George N.
Fournaris, Apostolos P.
Keywords: Cryptography
Hardware
Multiplication
Issue Date: 2009
Publisher: Elsevier
Source: Integration, the VLSI Journal, 2009, Volume 42, Issue 2, Pages 217-226
Abstract: High throughput is a crucial factor in bit-serial GF(2m) fields multiplication for a variety of different applications including cryptography, error coding detection and computer algebra. The throughput of a multiplier is dependent on the required number of clock cycles to reach a result and its critical path delay. However, most bit-serial GF(2m) multipliers do not manage to reduce the required number of clock cycles below the threshold of m clock cycles without increasing dramatically their critical path delay. This increase is more evident if a multiplier is designed to be versatile. In this article, a new versatile bit-serial MSB multiplier for GF(2m) fields is proposed that achieves a 50% increase on average in throughput when compared to other designs, with a very small increase in its critical path delay. This is achieved by an average 33.4% reduction in the required number of clock cycles below m. The proposed design can handle arbitrary bit-lengths upper bounded by m and is suitable for applications where the field order may vary.
URI: http://ktisis.cut.ac.cy/handle/10488/7305
ISSN: 01679260
DOI: 10.1016/j.vlsi.2008.07.003
Rights: © Elsevier B.V.
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