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|Title:||Intelligent on/off link management for on-chip networks||Authors:||Savva, Andreas
|Keywords:||Computer science;Neural networks;Networks on a chip;Hardware;Topology||Category:||Electronic Engineering,Electrical Engineering,Information Engineering||Field:||Engineering and Technology||Issue Date:||2011||Publisher:||IEEE Xplore||Source:||2011 IEEE Computer Society Annual Symposium on VLSI, (ISVLSI), 2011, Pages 343-344||Abstract:||Links connecting on-chip components are a major source of power consumption in modern-day on-chip interconnects. Several efforts have henceforth focused on reducing the power consumption, the majority of which efforts target selected links for turning on and off. In this paper we propose an intelligent power management policy for networks-on-chip where links are turned off and switched back on based on a neural network, which processes link utilization as feedback from the system and determines which links are candidates for turning off and back on. The neural network is kept relatively small in terms of area and power consumption, as it is used to forecast the optimal utilization threshold for which underutilized links are turned off||URI:||http://ktisis.cut.ac.cy/handle/10488/7115||ISBN:||978-1-4577-0803-9 (print)||ISSN:||978-0-7695-4447-2 (online)||DOI:||10.1109/ISVLSI.2011.13||Rights:||© Copyright 2011 IEEE||Type:||Book Chapter|
|Appears in Collections:||Κεφάλαια βιβλίων/Book chapters|
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