Please use this identifier to cite or link to this item: http://ktisis.cut.ac.cy/handle/10488/3747
Title: High-throughput hardware architectures of the JH round-three SHA-3 candidate: An FPGA design and implementation approach
Authors: Goutis, Costas E.
Athanasiou, George S. 
Chalkou, Chara I.
Bardis, D.
Michail, Harris 
Theodoridis, George
Keywords: Cryptographic primitives
Cryptographic schemes
FPGA design
Hardware architecture
High throughput
High throughput implementation
Implementation approach
International competitions
JH
National Institute of Standards and Technology
Proposed architectures
Security
Security protocols
SHA-3
Sha-3 candidates
Competition
Computer hardware
Cryptography
Field programmable gate arrays (FPGA)
Hardware
Network security
Hash functions
Issue Date: 2012
Source: International Conference on Security and Cryptography, Rome, Italy, 24-27 July, 2012
Abstract: Hash functions are exploited by many cryptographic primitives that are incorporated in crucial cryptographic schemes and commercial security protocols. Nowadays, there is an active international competition, launched by the National Institute of Standards and Technology (NIST), for establishing the new hash standard, SHA-3. One of the semi-finalists is the JH algorithm. In this paper, two high throughput hardware architectures of the complete JH algorithm are presented. The difference between them is the existence of 3 pipeline stages at the second one. They both are designed to support all the possible versions of the algorithm and are implemented in Xilinx Virtex-4, Virtex-5, and Virtex-6 FPGAs. Based on the experimental results, the proposed architectures outperform the existing ones in terms of Throughput/Area factor, regarding all FPGA platforms and JH algorithm's versions.
URI: http://ktisis.cut.ac.cy/jspui/handle/10488/3747
Appears in Collections:Δημοσιεύσεις σε συνέδρια/Conference papers

Show full item record

Page view(s)

1
checked on Jan 18, 2017

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.