Please use this identifier to cite or link to this item: http://ktisis.cut.ac.cy/handle/10488/1128
Title: Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks
Authors: Li-Shiuan, Peh 
Soteriou, Vassos 
Issue Date: 2007
Publisher: IEEE
Source: Parallel and Distributed Systems, IEEE Transactions on. Volume: 18, Issue: 3, pp. 1045-9219
Abstract: With power consumption becoming increasingly critical in interconnected systems, power-aware networks become part-and-parcel of many single-chip and multichip systems. As communication links consume significant power regardless of utilization, a mechanism to realize such power-aware networks is on/off links-network links that can be turned on/off as a function of traffic. In this paper, we investigate and propose self-regulating power-aware interconnection networks that turn their links on/off in response to bursts and dips in traffic in a distributed fashion. We explore the design space of such on/off networks, outlining a 5-step design methodology along with various building block solutions at each step that can be effectively assembled to develop various on/off network designs. We applied our methodology to the design of two classes of on/off networks with links that possess substantially different on/off delays, an on-chip network as well as a chip-to-chip network, and show that our designs are able to adapt dynamically to variations in network traffic. Three specific network designs are then constructed, presented, and evaluated. Our simulations show that link power consumption can be reduced by up to 54.4 percent, with a modest increase in network latency
URI: http://ktisis.cut.ac.cy/handle/10488/1128
ISSN: 1045-9219
DOI: 10.1109/TPDS.2007.43
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