Please use this identifier to cite or link to this item: http://ktisis.cut.ac.cy/handle/10488/1114
Title: Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Authors: Eisley, Noel A.
Wang, Hangsheng
Li, Bin
Peh, Lishiuan
Soteriou, Vassos 
Issue Date: 2007
Publisher: IEEE
Source: Computer Design, 2006. ICCD 2006. International Conference on, 2007. pp. 134-141
Abstract: Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, nigh-bandwidth network-on-chip (NoC) fabrics. As transistor feature sizes are further miniaturized leading to rapidly increasing amounts of on-chip resources, more complicated and powerful NoC architectures become feasible that can support more sophisticated and demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design space to identify the architecture(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris 1, a system-level roadmap for on-chip interconnection networks that guides designers towards the most suitable network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that will run over this network(s). Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While the Polaris roadmapping toolchain is extensible so new traffic, network designs, and processes can be added, the current version of the roadmap already incorporates 7,872 NoC design points. Polaris is rapid and iterates over all these NoC architectures within a tractable run time of 125 hours on a typical desktop machine, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.
URI: http://ktisis.cut.ac.cy/handle/10488/1114
ISBN: 9780780397071
ISSN: 1063-6404
DOI: 10.1109/ICCD.2006.4380806
Type: Conference Papers
Appears in Collections:Δημοσιεύσεις σε συνέδρια/Conference papers

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